产品详情

热销中 DP681TQFN46G-A0 谱瑞LCD时序控制器

Features

DisplayPort™ Input

Compliant to VESA® Embedded DisplayPort™ Standard 1.2

Supports VESA DPCD version 1.2

Supports 1-lane main link configuration and 2.7/1.62-Gbps data rate

Supports full link training, fast link training and no link training

Supports 18/24-bit RGB color format input

Supports DisplayPort™ standard SSC 0.5% down spreading

Content Protection

Supports eDP authentication: Alternate Scramble Reset (ASSR)

Panel Interface

Supports all sized panels up to one lane DisplayPort™ bandwidth limit, including HD (1366×768) and HD+ (1600×900) 6-bit panels

Supports Single bus, 3-pair, 6-bit mini-LVDS

Supports dynamic refresh rate (DRR), seamless Display Refresh Rate Switching (sDRRS) and nvDPS power saving modes

MiniLVDS interface pin swapping and internal data swapping for flexible TCON PCB design

Supports SINK additional SSC clock on miniLVDS interface: center spreading of 0.25% to 2.0%

TCON Interface

Supports dual gate pixel structure

Support special Z-Inversion pixel structure

Integrated programmable Gate Driver and Source Driver control signal generator

Fully programmable Gate Driver and Source Driver control I/O’s for GOP Applications.

Video Processing

CrystalFree technology – no external timing reference needed

Stores LUT contents in EEPROM to support gamma correction, color engine and FRC

Supports programmable BIST or Aging patterns

Backlight Control

Parade’s exclusive Smart-Backlight™1 feature for color and power optimization

Control Interface

I2C master for loading register initial values, or for expansion function

I2C slave for chip configuring, controlling and debugging

Integrated On-chip DC/DC switching regulator

Hardware driven power management

ESD HBM: 8000V for external connector pins, 7000V for all other pins; MM: 300V; CDM: 2000V